Quantum Computing

Quantinuum Announces Next Generation 32 Qubit H2 Processor With Application Research Results from Its Use


Photo Shows the Chip at the Heart of the H2 Processor with “Racetrack” Topology for Ion

Quantinuum has announced the H2 processor which they have had on their roadmap for a while. Current processors have 32 qubits and the capacity to process gate operations in four zones simultaneously. This continues with Quantinuum’s lead in qubit quality size and even increases their leading Quantum Volume (QV) size previously held by their H1-1 model with a QV of 65,536 in H2 versus the previous 32,768 in H1-1. The system is available now directly through Quantinuum and will also be available via Microsoft Azure’s quantum cloud in June. As with Quantinuum’s development approach with the H1 generation, the company hopes to continue improving its range of H2 models over the next year or two and hopes to have a version with more than 50 qubits by 2024. Like the H1 generation, the H2 also features all-to-all connectivity for qubits and also intermediate circuit measurements. A paper entitled Race Track Trapped Ion Quantum Processor explaining H2 has also been posted on arXiv.

While they continue to work on improved versions of the H2 generation, Quantinuum has already laid out the roadmap for the H3, H4, and H5 generations. Some of the technologies they will use for this include a grid based ion topology which will require movement of ions around 90 degree angles instead of just linear motion, integrated optics using photonic integrated circuits, shrinking control logic using application specific integrated circuits (ASICS), and so on scale up by creating modular ion trap chips that can be coupled together.

To demonstrate the capabilities of their ion trap-based architecture, Quantinuum has also posted several technical papers describing some of the original research done using the machine. First, they have demonstrated creating a 32 qubit GHZ state. This is a non-classical state with all 32 qubits entangled globally and is the largest GHZ state anyone has implemented so far. Furthermore, working with Harvard and Caltech, they have created the Non-Abelian Topological Order and demonstrated control over all of it. It has the potential to be used on fault tolerant computers. Developing a fault-tolerant architecture around topology principles has the potential to be more fault-resistant because state is not encoded by the physical state of a group of qubits, but rather as the overall topology of how the qubits are connected together. That has potentially significant advantages over other error correcting codes, such as surface code, and Quantinuum believes their architecture is far better suited to support this code than any other architecture. Microsoft is also researching topology-based qubits, but they are pursuing a different physical approach based on splitting the qubit between two Majorana zero modes (MZM). Quantinuum has posted a research paper on arXiv about their research titled Creation of Non-Abelian and Anyons Topological Sequences on Trapped-Ion Processors.

Other research papers based on experiments run on H2 include the one entitled Exploring 1-layer QAOA environments with Instant Quantum Polynomial circuits which leverages key Quantinuum processor features such as natively parameterized two-qubit gates and all-to-all connectivity to create enhanced variational quantum algorithms for solving combinatorial optimization problems. Other pieces of early research done on the H2 processor included paper from Global Technology Applied Research at JPMorgan Chase explaining the design of quantum algorithms for portfolio optimization.

To read more about the H2 Quantinuum announcement, you can view a copy of the press release Here. Quantinuum has also created a web page with links to all available H2-related technical papers, blog posts, and datasheets. Here.

May 9, 2023


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