CEA-Leti research scientists have shown that electrons and other charge carriers can move more quickly in germanium tin than in silicon or germanium, enabling lower operating voltages and a smaller footprint vertically than in planar devices. This proof-of-concept breakthrough means vertical transistors made of lead germanium are promising candidates for future low-power, high-performance chips and possibly quantum computers.
The Germanium–tin transistor exhibits electron mobility 2.5 times higher than a similar transistor made of pure germanium. GeSn is otherwise compatible with existing CMOS processes for chip manufacturing. Because germanium and tin come from the same periodic table group as silicon, these transistors can be integrated directly into conventional silicon chips with existing production lines.
A paper recently published in Nature Communications Engineering, Vertical GeSn Nanowire MOSFETs for Beyond Silicon CMOS, that note “GeSn alloys offer a tunable energy bandgap by varying the Sn content and adjustable band balancing in epitaxial heterostructures with Ge and SiGe. In fact, recent reports suggest that the use of Ge0.92sn0.08 as a source on top of the Ge nanowires (NWs) improve the performance of p-MOSFETs.”
“In addition to their unprecedented electro-optical properties, a key advantage of GeSn binaries is also that they can be embedded in the same epitaxy reactor as Si and SiGe alloys, enabling an all-group IV optoelectronic semiconductor platform that can be monolithically integrated on Ya,” paper report.
The project’s research included contributions from several organizations besides CEA-Leti, which delivered epitaxial stacks. Epitaxy is performed on a highly regular template, a silicon substrate, with a very precise crystal structure. By changing the material, CEA-Leti duplicates the crystal structure of its diamond in the layer it is placed on top of.
“Epitaxy is the art of creating multi-layers by duplicating original structures and is carried out at low temperatures with a gaseous precursor in a chemical vapor deposition reactor (CVD),” said Jean-Michel Hartmann, a CEA Fellow and team leader, group-IV epitaxy at CEA-Leti.
Depositing this type of pile and mastering the growth of the epitaxial layer is a very complex step in a process flow that requires patterned cylinders and deposition of conformal gate piles – in short, fabricating the entire device. CEA-Leti, one of the few RTOs globally capable of storing complex in-situ doped Ge/GeSn stacks, conducted part of the joint research reported in the paper.
“This collaboration demonstrates the potential of low-bandgap GeSn for advanced transistors with attractive electrical properties, such as high carrier mobility in the channel, low operating voltage, and a smaller footprint,” explained Hartmann, a co-author of the paper. “Industrialization is still far away. We are advancing the state of the art and demonstrating the potential of tin germanium as a duct material.”
The work also involved scientists from ForschungsZentrum Jülich, Germany; University of Leeds, United Kingdom; IHP- Innovations for High Performance Microelectronics, Frankfurt (Oder), Germany, and RWTH Aachen University, Germany.
Jean-Michel Hartmann accepts Electronics and Photonics Division Award at Electrochemical Society conference recently in Boston.
As recipient of the award, Hartmann presented a paper on May 30, Epitaxy of Group-IV Semiconductors for Nanoelectronics and Optoelectronics, covers how epitaxy can best be utilized to improve device properties.
Hartmann is a CEA Fellow at CEA-Leti, leader of the Epitaxy Working Group IV, and scientific director of the SSURF department. His research focuses on low pressure chemical vapor deposition of group-IV semiconductors for nanoelectronics and optoelectronics.