Biotechnology

Fast and compact transceiver for Sub-THz

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New transceiver designs capable of transmitting and receiving at frequencies over 100 GHz and data rates of 112 Gb/s could pave the way to 6G technology, scientists at Tokyo Tech report. By effectively suppressing self-interference caused by transmission signals leaking to the receiver, the proposed architecture achieves unprecedented data rates while maintaining an extremely compact size.

New transceiver designs capable of transmitting and receiving at frequencies over 100 GHz and data rates of 112 Gb/s could pave the way to 6G technology, scientists at Tokyo Tech report. By effectively suppressing self-interference caused by transmission signals leaking to the receiver, the proposed architecture achieves unprecedented data rates while maintaining an extremely compact size.

Scientists and engineers in the telecommunications field are already working on the technology that will be used for sixth generation (6G) networks. Ideally, 6G should provide data rates of over 100 gigabits per second (Gb/s) and support very low latency for applications such as autonomous cars and virtual reality. One way to meet these massive transmission and reception needs is to adopt a full-duplex (FD) architecture that operates at sub-THz frequencies from 88 to 136 GHz.

The main advantage of the FD architecture is that it allows a single system to transmit and receive signals, effectively doubling the throughput. One way to implement this architecture is to have the transmitting and receiving modules share a single antenna. This helps reduce circuit size and allows both halves to take full advantage of the available frequency spectrum.

However, single-antenna FD architectures suffer greatly from self-interference (SI), a phenomenon in which the transmitted signal leaks to the receiving side. The system must include a circuit for SI cancellation that attempts to cancel the SI generated by injecting the same signal of opposite polarity. In the sub-THz band, implementing effective SI cancellation is much more challenging than at lower frequencies, which remains a hurdle for single-antenna FD designs.

Against this backdrop, a research team from Tokyo Institute of Technology (Tokyo Tech), Japan, recently developed a new FD communication system that overcomes the barriers posed by SI. Professor Kenichi Okada’s research team will present their design in the future 2023 Symposium on VLSI Technologies and Circuits held June 11-16, Kyoto, Japan.

One of the main features of their system is the implementation of a dual polarized patch antenna. It is driven by a differential signal—a combination of positive and negative charging ports for transmitting and receiving. By making the circuit paths of these ports strictly symmetrical, transmitted signal mismatches leaking to the differential receiving ports are minimized, which helps to keep SI low. “Our design avoids large transmission leaks which are common in devices with asymmetric antenna structures and asymmetric differential signal ports,” explained Prof. Okada.

Another important aspect of the proposed design is the SI cancellation circuit (SIC). To effectively cancel the resulting SI, one needs to carefully modify the phase of the canceling signal so that it is opposite to that of the leaking signal. This is usually done using a variable capacitor called a varactor. However, in the sub-THz range, conventional varactors have a limited phase range and poor resolution. To solve this problem, the researchers developed a new varactor structure that achieves excellent linear resolution across the sub-THz band and across the full 360° range.

The team tested their design through a series of trials, which yielded some promising results. “In over-the-air measurements, the proposed FD transceiver achieves 6 Gb/s. SI suppression is increased by 20 decibels when SI cancellation is turned on, ”said Prof. Okada.

The device, the world’s first FD phased-array transceiver operating at over 100 GHz, also achieves data rates of 112 Gb/s in HD mode. It is the fastest system among sub-THz phased array transceivers. Together with the compact size and wide operating frequency range, the proposed architecture is a major step towards telecommunications technology for 6G.

Let’s hope that further research in this direction brings us closer to a more interconnected world!

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Confession

This work was partially supported by the Ministry of Internal Affairs and Communications in Japan (JPJ000254).

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  • Okada Laboratory.
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  • New and Improved Multi-Band Operational Receiver for New 5G Radio Communications | Tokyo Technology News
  • Three Members of Tokyo’s Faculty of Technology Receive IEEE 2023 Fellowships | Tokyo Technology News
  • Kenichi Okada – Connecting the world wirelessly | The Story of Tokyo Technology Research

About the Tokyo Institute of Technology

Tokyo Tech stands at the forefront of research and higher education as the leading university for science and technology in Japan. Tokyo Tech researchers excel in fields ranging from materials science to biology, computer science, and physics. Founded in 1881, Tokyo Tech hosts over 10,000 undergraduate and graduate students annually, who develop into scientific leaders and some of the most sought-after engineers in the industry. Embodying the Japanese philosophy of “monotsukuri”, which means “technical intelligence and innovation”, the Tokyo Technology community strives to contribute to society through high-impact research.

https://www.titech.ac.jp/english/


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